This invention generally relates to a designing of an integrated circuit (IC) or a large-scale integrated circuit (LSI), and specifically relates to a logic design system for transforming a logic circuit of imaginary elements into a logic circuit of actual elements, or transforming a logic circuit of actual elements into another logic circuit of actual elements. This invention also relates to a method used in such a logic design system.
Generally, a top-down technique is used in a designing of an LSI. In such a top-down technique, the details of required functions are first identified and then a structure corresponding to the required functions is written in a primitive logic circuit, and the primitive logic circuit is transformed into an actual, physical logic circuit composed of actual elements.
It is well-known that a designing of an LSI which is based on a top-down technique is realized by a computer-based designing system. The computer-based designing system transforms a description of functions by a higher computer language such as "Prolog" or "C" into a logic-element circuit level, and transforms the logic-element circuit level into an actual-element circuit level.
The collection of papers related to the lectures in National Meeting of Japanese Society of Information Processing, 1985, pages 1923-1926, shows a circuit transformation technology in which a logic circuit containing theoretical, hypothetical, or imaginary logic elements is transformed into a logic circuit composed of only actual logic elements. Specifically, a prior-art logic design system based on this circuit transformation technology prestores information of logic elements containing imaginary logic elements, and also information of the relations between the logic circuits and corresponding actual logic circuits. The latter information is called "circuit transformation information". When information of a logic circuit containing imaginary logic elements is inputted into the logic design system, the following processes are executed by the logic design system. The respective logic elements of the input logic circuit are collated with the prestored logic elements, and actual-element logic circuits are sequentially generated for the respective logic elements of the input logic circuit by referring to the circuit transformation information. The input logic element and its fan out are considered in the generation of a corresponding actual-element logic circuit.
The above-mentioned prior-art logic design system has the following problem. Since the transformation of each input logic element into a corresponding actual-element logic circuit is fixed, a circuit transformation can not be performed in consideration of an observation of the circuit structure synthesized thereby. Accordingly, a resultant of the actual-element logic circuits tends to be more redundant than that obtained by a skilled circuit designer.
This problem of the prior-art logic design system is resolved by a logic design system disclosed in Japanese published unexamined patent application 59-168545. The logic design system of Japanese patent application 59-168545 prestores information related to a skilled circuit designer's knowledge of optimizing a circuit transformation in dependence on conditions of connections of logic elements. A circuit transformation process is performed by referring to this knowledge base, and thus the optimization of the circuit transformation is realized.
The knowledge base has components which are provided in correspondence with respective logic elements containing imaginary logic elements. Each component of the knowledge base includes a combination of circuit transformation rules. Each circuit transformation rule has a condition part and a conclusion part. The condition part relates to conditions of connections in an input logic element. The conclusion part relates to circuit transformation operations corresponding to the condition part. During the execution of the circuit transformation process, with respect to an input logic element, the component of the knowledge base which corresponds to the input logic element is referred to. Subsequently, the circuit transformation rules forming the component of the knowledge base are successively analyzed by an interpreter, and conditions of connections in the input logic element are sequentially collated with the condition parts of the circuit transformation rules to find the condition part of the circuit transformation rule which matches with the conditions of the connections of the input logic element. Finally, the circuit transformation is performed in accordance with the conclusion part of the circuit transformation rule whose condition part matches with the conditions of the connections of the input logic element.
Most prior art technologies of designing a logic circuit do not consider the optimization of signal delay times in a finally-obtained actual-element circuit. Only a few of the prior art technologies consider the optimization of signal delay times. For example, a signal delay time is evaluated on the basis of the number of logic stages (logic levels) of logic elements in a logic circuit.
Technical Study Report, Vol. 87 No. 92 (1987), pages 9-16, in Japanese Society of Electronics, Information, and Communications, discloses an example of a prior art designing of a logic circuit which considers the optimization of a signal delay time in a finally-obtained actual-element circuit. In this prior art designing technique, during a circuit transformation, a signal delay time is considered by giving predicted delay times to logic elements respectively, and calculating the longest path among a register and input and output terminals in a logic circuit. Such a process of evaluating a delay time is started from an output terminal side. When the delay evaluating process is advanced to a given logic element, the sum of the longest path from the given logic element to the output terminal and the predicted longest path from the input terminal to the given logic element is calculated, and the calculated sum is compared with a designated value. If the calculated sum exceeds the designated value, the related circuit transformation is not adopted.
The previously-mentioned prior art technologies have problems as follows. In the prior art technologies, during a circuit transformation, a signal delay time is evaluated on the basis of the number of logic stages .(logic levels) or the sum of predicted delay times given to respective logic elements, and the accuracy of the evaluation tends to be low since the logic stages (logic levels) and the logic elements are different from actual circuit elements. Further, in the prior art designing of the previously-mentioned Technical Study Report, since a process of evaluating a signal delay time is started from an output terminal side, it is generally difficult to execute a global optimization of a signal delay time which takes the whole of a circuit structure into consideration. Therefore, in some cases, a finally-obtained logic circuit is not optimal in a signal delay time.
Logic design systems according to the prior art technologies can not consider timing conditions determined by factors such as a setup time and a hold time of registers. Therefore, in the prior art logic design systems, an optimization of timing conditions has only an object of decreasing a signal delay by the longest path in a logic circuit, and it is difficult to execute an optimization of timing conditions in a sequential logic circuit. Further, the prior art logic design systems lack a function of correcting an error of timing conditions which is found during the check of the timing conditions in a finally-obtained actual-element circuit.